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Host Port Signals
6.2 Host Port Signals
The host port signals are discussed in Chapter 2 , Signals/Connections . Each host port signal can
be programmed as a host port signal or as a GPIO signal, PB[0–15]. See Table 6-1 through
Table 6-3 .
Table 6-1. HI08 Signal Definitions for Operational Modes
HI08 Port Signal
HAD[0–7]
HAS/HA0
HA8/HA1
HA9/HA2
HCS/HA10
Multiplexed Address/Data Bus Mode
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Non-multiplexed Bus Mode
H[0–7]
HA0
HA1
HA2
HCS/HCS
GPIO Mode
PB[0–7]
PB8
PB9
PB10
PB13
Table 6-2. HI08 Data Strobe Signals
HI08 Port Signal
HRW/HRD
HDS/HWR
Single Strobe Mode
HRW
HDS/HDS
Dual Strobe Mode
HRD/HRD
HWR/HWR
GPIO Mode
PB11
PB12
Table 6-3. HI08 Host Request Signals
HI08 Port Signal
HREQ /
Single Host Request Mode
HREQ/HREQ
Double Host Request Mode
HTRQ/HTRQ
GPIO Mode
PB14
HTRQ
HACK/
HACK/HACK
HRRQ/HRRQ
PB15
HRRQ
The HI08 port can operate in multiplexed or non-multiplexed mode. In multiplexed mode
(HPCR[11]:HMUX = 1), the lower eight address signals multiplex with the eight data lines. In
non-multiplexed mode (HPCR[11]:HMUX = 0), the HI08 requires a chip select signal and three
address lines to select one of the eight registers accessible to the host. Eight lines are used for
data. The HI08 port can also be programmed to use a single or dual read/write data strobe and
single or double host request.
Software and hardware resets clear all DSP-side control registers and configure the HI08 as
GPIO. To select GPIO functions, clear HPCR bits 6 through 1; to select other HI08 functions, set
those same bits. If the HI08 is in GPIO mode, the HDDR configures each corresponding signal in
the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is
set. For details, see Section 6.6.3 , Host Data Direction Register (HDDR) , on page 6-14 and
Section 6.6.4 , Host Data Register (HDR) , on page 6-15.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
6-3
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